;PALASM Design Description

;---------------------------------- Declaration Segment ------------
TITLE    decode.pds
PATTERN  B
REVISION 1.1
AUTHOR   Matti Aarnio
COMPANY  HamProject
DATE     920317

CHIP  decode  PAL22V10

;---------------------------------- PIN Declarations ---------------
PIN   1 /HOSTENA        COMBINATORIAL   ; INPUT 
PIN   2..9 A[14..7]     COMBINATORIAL   ; INPUT 
PIN  10 SIZE32KB        COMBINATORIAL   ; INPUT
PIN  11 PA14            COMBINATORIAL   ; INPUT
PIN  12 Gnd                             ;
PIN  13 /RD             COMBINATORIAL   ; INPUT
PIN  14 /RAMCS          COMBINATORIAL   ; OUTPUT
PIN  15 /DDLC1CS        COMBINATORIAL   ; OUTPUT
PIN  16 /DDLC2CS        COMBINATORIAL   ; OUTPUT
PIN  17 /CTRLREAD       COMBINATORIAL   ; OUTPUT
PIN  18 /CTRLWRITE      COMBINATORIAL   ; OUTPUT
PIN  19  RAMSEL         COMBINATORIAL   ; loopback
PIN  20  A14            COMBINATORIAL   ; OUTPUT (3-state)
PIN  21 /BUFENA         COMBINATORIAL   ; OUTPUT
PIN  24 Vcc                             ;        

;----------------------------------- Boolean Equation Segment ------
EQUATIONS

MINIMIZE_OFF
;         When SIZE32KB is high, used size is 32kB, othervice 16kB.
RAMSEL    = /A[9] * /A[10] * /A[11] * /A[12] * /A[13] *         /SIZE32KB +
            /A[9] * /A[10] * /A[11] * /A[12] * /A[13] * /A[14] * SIZE32KB
RAMCS     =               /RAMSEL
DDLC1CS   =      HOSTENA * RAMSEL * /A[7] * /A[8]
DDLC2CS   =      HOSTENA * RAMSEL *  A[7] * /A[8]
CTRLREAD  =      HOSTENA * RAMSEL * /A[7] *  A[8] * /RD
CTRLWRITE =      HOSTENA * RAMSEL * /A[7] *  A[8] *  RD
BUFENA    =      HOSTENA
A14       =      PA14
A14.TRST  =      BUFENA ; Have that small delay in it.. All others have it too

;----------------------------------- State Segment -----------------
;STATE

;----------------------------------- Simulation Segment ------------
SIMULATION
TRACE_ON     A14

; Test PA14 -> A14 with 3-state control
SETF /HOSTENA PA14
CHECK ^A14
SETF HOSTENA PA14
CHECK A14
SETF HOSTENA /PA14
CHECK /A14
TRACE_OFF

TRACE_ON /RAMCS /DDLC1CS /DDLC2CS /BUFENA /CTRLREAD /CTRLWRITE

; All inactive
SETF /HOSTENA /A[7] /A[8] /A[9] /A[10] /A[11] /A[12] /A[13] /A[14] SIZE32KB /RD
CHECK /RAMCS /DDLC1CS /DDLC2CS /BUFENA /CTRLREAD /CTRLWRITE
SETF /HOSTENA /A[7] /A[8] /A[9] /A[10] /A[11] /A[12] /A[13] A[14] /SIZE32KB /RD
CHECK /RAMCS /DDLC1CS /DDLC2CS /BUFENA /CTRLREAD /CTRLWRITE

; RAMCS ok, others inactive
SETF /HOSTENA /A[7] /A[8]  A[9] /A[10] /A[11] /A[12] /A[13] /A[14] SIZE32KB /RD
CHECK RAMCS /DDLC1CS /DDLC2CS /BUFENA /CTRLREAD /CTRLWRITE

; Another RAM activation(s)
SETF /HOSTENA /A[7] /A[8] /A[9] /A[10] /A[11] /A[12] /A[13] A[14] SIZE32KB /RD
CHECK RAMCS /DDLC1CS /DDLC2CS /BUFENA /CTRLREAD /CTRLWRITE
;SETF /HOSTENA A[7] A[8] /A[9] /A[10] /A[11] /A[12] /A[13] /A[14] SIZE32KB /RD
;CHECK RAMCS /DDLC1CS /DDLC2CS /BUFENA /CTRLREAD /CTRLWRITE
SETF /HOSTENA /A[7] A[8] A[9] A[10] A[11] A[12] A[13] /A[14] SIZE32KB /RD
CHECK RAMCS /DDLC1CS /DDLC2CS /BUFENA /CTRLREAD /CTRLWRITE

; HOST accessing IO devices
SETF HOSTENA /A[7] /A[8] /A[9] /A[10] /A[11] /A[12] /A[13] /A[14] SIZE32KB /RD
CHECK /RAMCS DDLC1CS /DDLC2CS BUFENA /CTRLREAD /CTRLWRITE
SETF HOSTENA  A[7] /A[8] /A[9] /A[10] /A[11] /A[12] /A[13] /A[14] SIZE32KB /RD
CHECK /RAMCS /DDLC1CS DDLC2CS BUFENA /CTRLREAD /CTRLWRITE
SETF HOSTENA /A[7] A[8] /A[9] /A[10] /A[11] /A[12] /A[13] /A[14] SIZE32KB /RD
CHECK /RAMCS /DDLC1CS /DDLC2CS  BUFENA  CTRLREAD /CTRLWRITE
SETF HOSTENA /A[7] A[8] /A[9] /A[10] /A[11] /A[12] /A[13] /A[14] SIZE32KB  RD
CHECK /RAMCS /DDLC1CS /DDLC2CS BUFENA /CTRLREAD CTRLWRITE

SETF HOSTENA /A[7] /A[8] /A[9] /A[10] /A[11] /A[12] /A[13] /A[14] /SIZE32KB /RD
CHECK /RAMCS  DDLC1CS /DDLC2CS BUFENA /CTRLREAD /CTRLWRITE
SETF HOSTENA /A[7] /A[8] /A[9] /A[10] /A[11] /A[12] /A[13]  A[14] /SIZE32KB /RD
CHECK /RAMCS  DDLC1CS /DDLC2CS BUFENA /CTRLREAD /CTRLWRITE
TRACE_OFF

TRACE_ON /RAMCS /DDLC1CS /DDLC2CS /BUFENA /CTRLREAD /CTRLWRITE

; DDLC accessing memory
SETF /HOSTENA /A[7]  A[8]  A[9]  A[10]  A[11]  A[12]  A[13]  A[14] SIZE32KB
CHECK  RAMCS /DDLC1CS /DDLC2CS /BUFENA /CTRLREAD /CTRLWRITE
SETF /HOSTENA /A[7]  A[8]  A[9]  A[10]  A[11]  A[12]  A[13]  A[14] SIZE32KB
CHECK  RAMCS /DDLC1CS /DDLC2CS /BUFENA /CTRLREAD /CTRLWRITE
SETF /HOSTENA /A[7]  A[8]  A[9] /A[10] /A[11] /A[12] /A[13] /A[14] SIZE32KB
CHECK  RAMCS /DDLC1CS /DDLC2CS /BUFENA /CTRLREAD /CTRLWRITE
SETF /HOSTENA /A[7] /A[8] /A[9] /A[10] /A[11] /A[12] /A[13] /A[14] SIZE32KB
CHECK /RAMCS /DDLC1CS /DDLC2CS /BUFENA /CTRLREAD /CTRLWRITE

; HOST accessing memory (should test more ?)
SETF  HOSTENA /A[7]  A[8]  A[9]  A[10]  A[11]  A[12]  A[13] /A[14] SIZE32KB
CHECK  RAMCS /DDLC1CS /DDLC2CS  BUFENA /CTRLREAD /CTRLWRITE

SETF  HOSTENA /A[7]  A[8]  A[9]  A[10]  A[11]  A[12]  A[13] /A[14] SIZE32KB
SETF  HOSTENA /A[7]  A[8]  A[9]  A[10]  A[11]  A[12]  A[13] /A[14] SIZE32KB

TRACE_OFF

;-------------------------------------------------------------------